1. Field of the Invention
The present invention is directed toward the field of power regulation, specifically integrated linear voltage regulators.
2. Art Background
Modern VLSI systems tend toward low cost-of-manufacture designs with low power consumption. Complementary metal-oxide semiconductor (CMOS) fabrication technology is particularly attractive: it is relatively low-cost, has high-performance, and permits the integration of many device functionalities on a single chip.
Many CMOS applications would benefit from on-chip linear voltage regulation to convert relatively higher supply voltage to a lower operating voltage, e.g. 1.5 V supply to 1 V operating. This would allow the use of newer CMOS technologies, resulting in lower power consumption. For example, a fully buffered dual in-line memory module (FBDIMM) supplements dynamic random access memory (DRAM) capacity of a computer system. The Joint Electron Device Engineering Council (JEDEC) FBDIMM specification, JESD 82-20, “FBDIMM: Advance Memory Buffer (AMB),” calls for an on-board supply voltage of 1.5 V for the Advanced Memory Buffer (AMB) with high-speed serial links between the Host and the AMB may operate at 3.2/4.0/4.8 Gigabits per second. A 1.5 V design, i.e. without regulating the supply voltage down, would require at least 0.13 μm CMOS technology.
However, integration of traditional linear voltage regulator designs would pose several challenges. First, feedback control loops must be stabilized over a wide range of load current conditions without compromising bandwidth. Second, because low power design schemes often operate power-hungry blocks with lower duty cycles, requiring fast turn-on/off transients, regulator designs must be extremely agile and tolerant of dramatic changes in load current. In the FBDIMM spec, for example, the AMB device may have only 100 nanoseconds to transition into, and out of, a low-power ‘L0s’ state. In essence, low power operating schemes tend to exacerbate an already challenging design problem, rendering traditional linear voltage regulator designs unsuitable for CMOS integration.
Specifically, FIG. 1 shows a conventional linear voltage regulator design. The current source 100 supplies the dynamic load 110. An analog error amplifier 130 senses the residual difference between the power supply voltage of the current source 100, which is the voltage being regulated, and an ideal reference voltage produced by the source 120. Based on this residual, the amplifier 130 produces an analog control voltage that is supplied to the current source 100. The current source 100 adjusts its strength based on the control voltage to drive the residual error to zero.
There are at least two major requirements for most linear voltage regulators: first, the regulator feedback loop, here the path between the current source 100 and the error amplifier 130, must be stable over various load conditions; second, the regulator feedback loop may need to be agile to adapt to a rapidly changing current load.
Often, these are conflicting requirements. There are usually at least two major poles in this feedback system—at the input and the output of the analog amplifier. First, there is usually a large fixed-bypass capacitor that sits on the power supply node for high-frequency power supply noise rejection. The large capacitor (150 in FIG. 1), together with the variable resistance of a dynamic load, results in a major pole in the feedback system. Additionally, the output of the analog amplifier usually has large output resistance to ensure that the loop gain is sufficiently large for small residual error. This output node also has some parasitic capacitance (140 in FIG. 1), resulting in yet another major pole in the system. The variability of the dynamic load may cause the position of first major pole to vary significantly. To make the stability of the feedback system robust to such variation, designers may choose to make the second pole the ‘dominant’ one by making capacitor 140 larger. This results in lower bandwidth and slower response times for the linear voltage regulator. As a result, stabilizing this system over a wide variety of loading conditions, without compromising bandwidth, is a difficult task.
To make things worse, in aggressive power conservation schemes in modern low-power VLSI systems, the current load may change from a ratio of 3:1 or more, over an extremely short time interval. Under such conditions, satisfying both these requirements may prove to be a daunting task.